I'm having big troubles with PACE in ISE 13.2. Game Motogp Terbaru Gratis. Here's how to reproduce: 1. Open the jc2_svhd example project 2. Remove the included user constraints file (jc2_top.ucf) 3. Run the Floorplan IO - Pre-Synthesis process, creating a new UCF file ->The I/O pins listed in PACE have basically no relation to the design. If you omit step 2 above, PACE instead spits out these error messages: Compiling vhdl file 'C:/Users/anders/xilinx/test/jc2_svhd/jc2_top.vhd' inLibrary work.

Entity compiled. Entity (Architecture ) compiled. Entity compiled. Entity (Architecture ) compiled. Entity compiled. Entity (Architecture ) compiled. ERROR:DesignEntry - Could not apply constraint: NET left LOC=G7; ERROR:DesignEntry - Could not apply constraint: NET right LOC=B2; ERROR:DesignEntry - Could not apply constraint: NET stop LOC=F2; ERROR:DesignEntry - Could not apply constraint: NET clk LOC=A7; ERROR:DesignEntry - Could not apply constraint: NET q LOC=B4; ERROR:DesignEntry - Could not apply constraint: NET q LOC=C6; ERROR:DesignEntry - Could not apply constraint: NET q LOC=F6; ERROR:DesignEntry - Could not apply constraint: NET q LOC=G5; This happens in all designs that use a top-level schematic.